1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a semiconductor device having a metal silicide layer on an element region and a method of manufacturing the semiconductor device. For example, the present invention is applied to a complementary metal-oxide-semiconductor (CMOS) logic large-scale integration (LSI).
2. Description of the Related Art
For example, in the CMOS logic LSI, a self-aligned silicide (salicide) technique is used to suppress a parasitic resistance, which increases as a device is miniaturized. In the salicide technique, a reaction product between a metal and a semiconductor such as Si, namely, a silicide compound (hereinafter, referred to as a “metal silicide”), is formed on the source/drain region (an impurity diffusion layer formed in a semiconductor substrate) of a metal oxide semiconductor field-effect transistor (MOSFET) and on the gate electrode formed of a polycrystalline Si. By virtue of the presence of the metal silicide, the resistivity of each of the source/drain region and the gate electrode can be reduced. In this case, the metal to be used in the metal silicide is chosen based on a desired resistance value in consideration of conditions such as a thermal design of a CMOS process, the dimension of the gate electrode, and the depth of the diffusion layer.
Incidentally, in a CMOS technique developed after a 65 nm-node technology, a low temperature processing is required for a process forming a metal silicide in order to suppress a metal material from causing thermal diffusion, thereby suppressing contact current leakage taking place in the impurity diffusion layer and in order to suppress the doped n-type and p-type impurities from being activated. To reduce the temperature, attention has been focused on Ni. This is because Ni monosilicide can reduce the resistivity, unlike Ti and Co. Therefore, Ni is a metal material, which attains film formation at low temperature.
However, the diffusion coefficient of Ni in Si is large, which means that the chemical reaction between Si and Ni proceeds while Ni is being diffused in Si during the silicide formation process. Accordingly, when unreacted Ni is present excessively around the reaction region, the thickness of a Ni film around the reaction region increases. When a silicide is formed, excessive Ni is diffused into the element region, with the result that a silicide reaction excessively takes place in the contact region. It follows that contact current leakage takes place in the gate electrode or the impurity diffusion layer in the source/drain region. In short, current leakage occurs due to the presence of a metal silicide formed in the contact region.
When a Ni silicide is formed on the gate electrode and the source/drain region of a MOSFET by a conventional salicide technique, contact current leakage sometimes occurs depending upon the area ratio between the silicide reaction region, which is formed on the gate electrode and the source/drain region, and the silicide unreaction region, which is formed on a shallow trench isolation (STI).
FIG. 1 is a schematic plan view showing a pattern where Ni-silicide is formed in a relatively large element region (AA) 211 of an STI region 201 of a semiconductor substrate. FIG. 2 shows a schematic sectional view of the pattern. Similarly, FIG. 3 shows a schematic plan view showing a pattern where Ni-silicide is formed in a small element region (AA) 212 isolated like an island in a relatively large STI region 201 of the substrate. FIG. 4 is a schematic sectional view of the pattern.
In FIGS. 1 to 4, reference numerals 200, 201, 202, 203 and 204 denote an n-type Si substrate, STI region, p-well, n+-diffusion layer, and Ni-silicide, respectively.
As shown in FIGS. 1 and 2, when the Ni silicide 204 is formed in the relative large element region 211, there is no problem since the chemical reaction of Ni proceeds uniformly in the element region 211. Whereas, as shown in FIGS. 3 and 4, when the Ni silicide 204 is formed in the small element isolation region 212 which is discretely present like an island in the relatively large STI region 201, excess Ni present in the STI 201 (unreaction region) around the element region 212 diffuses into the element region 212 during processing, with the result that an excessive silicide reaction proceeds in the depth direction of the contact region, causing contact current leakage.
Note that U.S. Pat. No. 6,180,469 discloses a technique for reducing contact current leakage and resistance. The technique includes selectively forming a Ni layer on the surfaces of the gate electrode and the source/drain region by electroless plating, doping N ions in the Ni layer to form a barrier layer, which divides the Ni layer into upper and lower layers, and applying heat treatment to the lower Ni layer, thereby converting only the lower Ni layer into a silicide layer.
As described, a conventional semiconductor device has a problem in that when Ni silicide is formed in the element region surrounded by the STI by the salicide technique, more specifically, in the element region formed discretely like an island in a large STI region, Ni excessively present in an unreaction region diffuses into the element region during the silicide process, suppressing an excessive silicide reaction in the contact region, thereby causing contact current leakage.